Fast fixed-point bicubic interpolation algorithm on FPGA
Koljonen, Janne; Bochko, Vladimir A.; Lauronen, Sami J.; Alander, Jarmo T. (2019-11-21)
Koljonen, Janne
Bochko, Vladimir A.
Lauronen, Sami J.
Alander, Jarmo T.
Editori(t)
Nurmi, Jari
Ellervee, Peeter
Halonen, Kari
Röning, Juha
Institute of Electrical and Electronics Engineers (IEEE)
21.11.2019
Julkaisun pysyvä osoite on
https://urn.fi/URN:NBN:fi-fe202002135388
https://urn.fi/URN:NBN:fi-fe202002135388
Kuvaus
vertaisarvioitu
Tiivistelmä
We propose a fast fixed-point algorithm for bicubic interpolation on FPGA. Bicubic interpolation algorithms on FPGA are mainly used in image processing systems and based on floating-point calculation. In these systems, calculations are synchronized with the frame rate and reduction of computation time is achieved designing a particular hardware architecture. Our system is intended to work with images or other similar applications like industrial control systems. The fast and energy efficient calculation is achieved using a fixed-point implementation. We obtained a maximum frequency of 27.26 MHz, a relative quantization error of 0.36% with the fractional number of bits being 7, logic utilization of 8%, and about 30% of energy saving in comparison with a C-program on the embedded HPS for the popular Matlab test function Peaks(25,25) data on SoCkit development kit (Terasic), chip: Cyclone V, 5CSXFC6D6F31C8. The experiments confirm the feasibility of the proposed method.
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