ARM RDN2 and TSS Integration as a System-on-Chip Simulation

Abstract

System-on-Chip (SoC) technology plays a key role in modern electronic devices by making them smaller, faster, and more energy-efficient. It facilitates this by combining all the main components such as processors and memory into a single chip. Today, SoCs are used in many areas like smartphones, cars, airplanes, and other embedded systems. However, traditional verification methods struggle to detect hardware-software integration issues effectively in early development stages as systems become more complex. One challenge is to detect integration problems between hardware and software components at early stages.

This thesis focuses on challenges of the traditional methods by creating a new co-simulation approach. The aim is to use data processing unit that supports up to date ARM processors architecture while keeping the flexibility advantages of Target SoC Simulator (TSS) by replacing QEMU in current framework. Since ARM Fast Models support the latest ARM processor architectures, a platform based on Fast Models was integrated into the framework. As a proof of concept, the ARM Reference Design N2 (RDN2) was selected. The approach is to integrate the ARM RDN2 platform with the TSS to use advantages from both platforms.

This thesis mainly explores two primary research questions: Can the ARM RDN2 platform be integrated into the TSS environment without changing the original structure of TSS, and will the combined system maintain synchronization and correct functionality? To answer these questions, a systematic methodology was used. The methodology involved tool selection, integration of platforms through a special interface wrapper for data transfer and testing to ensure synchronization.

Results of the early tests showed that the system worked properly. The data was correctly transferred between TSS and ARM RDN2 while both platforms maintaining synchronization by 1 microsecond. This means that the framework is useful for testing hardware and software together before the real silicon is ready. These results suggest that the system can help make SoC design more accurate and reduce development time and cost.

Despite these advantages, there were some limitations identified. Integration was complex due to differences in transaction formats and timing models used by TSS and RDN2. Additionally, the system currently lacks interrupt support. Future research should focus on testing this integration with more complex systems, optimizing data transfer speeds, and adding interrupt handling capabilities. This integrated system is a promising way to test precise and reliable early validation in the development of advanced SoC systems. This integration specifically beneficial in fast-paced industries like telecommunications.