Efficient Implementation of Searchless Fractal Image Compression on Low-cost FPGA for Real-Time Encoding

Abstract

Self-similarity within images is utilized by Fractal Image Compression (FIC) method to provide potential benefit of high compression ratio, good recovery performance, flexible recovery resolution, and fast decoding process. Nevertheless, FIC has a significant drawback—its encoding process is highly time-consuming, particularly when a full-search approach is employed. To address this issue, searchless-based approaches have been developed and implemented in hardware to enable real-time encoding. Despite their advantages, existing hardware designs often require significant hardware resources, making them unsuitable for low-cost FPGA platforms. In this paper, a real-time andhardware-effecient architecture is proposed for encoding images with searchless-based FIC method, optimized for low resource utilization. The proposed design encoded the image blocks in different sizes based on quadtree approach. The design was synthesized and implemented on a low-cost FPGA, with circuit-level optimizations using parallelism and pipelining to enable real-time image encoding. Its performance was quantitatively assessed based on encoding time, hardware resource utilization, peak signal-to-noise ratio (PSNR), and compression ratio. With an operating frequency of 50 MHz, a run time of 9.65 ms can be achieved for an 512×512×8 image, which is equivalent to 103 images which can be encoded per second. The design consumes less than half of the total device resource in the low-cost Cyclone V SoC FPGA. The average PSNR and compression ratio achieved are 32 dB and 14:1 respectively