Implementation of Genetic Algorithms on an FPGA Ethernet Tester

In electrical substation automation systems (SAS), intelligent electronic devices (IED) communicate over Ethernet within the IEC 61850 standard. The main objective of the standard is to bring compatibility, security and robustness between different IEDs, regardless the manufacturer. A typical SAS consists of IEDs such as circuit breakers, protection relays and controllers. This thesis concerns the generation and transmission of Ethernet traffic from a Field Programmable Gate Array (FPGA) to an IED. The research question was to study the robustness of the IEC 61580 standard implementation on an IED and search for Ethernet data that might be harmful for the device. An FPGA, with high speed performance due to its parallelism, combined with a genetic algorithm search optimization process, was chosen to approach the problem. Genetic algorithms are optimization methods which have taken inspiration from biology, where species strive for survival. In this research case, genetic algorithms were implemented in an FPGA where they are adapted to the Ethernet frames by means of recombination and mutation of binary data. Transmission-round trip time feedbacks were measured by an external device, where a larger transmission time results in a greater fitness value, gaining a higher probability of finding harmful data. The result was a hardware implementation of genetic algorithms on an FPGA platform that manages to transmit Ethernet frames at high speed. In the research it was also obtained that it is possible to cause an IED to crash depending on Ethernet frame data and transmission speed.